Field of the Invention
The present invention relates to a coil and to a coil system for integration into a microelectronic circuit. Furthermore, the invention relates to a microelectronic circuit.
Inductances (coils) are required in a multitude of circuit types, for example in oscillators, amplifiers, mixers or the like. The inductances, i.e., inductors, belong to the component types whose integration on a chip together with the remaining circuit parts can give rise to problems. To date this has meant that inductances are in many cases still used as discrete components, since they would otherwise have disadvantages as coil forms integrated on chips. At very high frequencies, that is to say at frequencies in ranges far above 1 GHz, integrated inductances have to be used in any case since signal transmission then becomes very difficult via the leads of the discrete coils.
FIG. 1 illustrates a typical coil implementation as it is known from the prior art. A metal track runs through a spiral, thereby producing a number of turns with increasing radii. If a plurality of metal layers are available on the chip, such spirals can be stacked. The inductances add up through connection in series. Track resistances are reduced in the event of connection in parallel, which leads to lower power losses. However, these known coils, or coil forms, have a series of disadvantages. A particular disadvantage results, for example, from the punch-through of the magnetic field into the substrate, usually a silicon substrate. Generally, in modern CMOS technologies, a relatively low-impedance substrate is used, which results in a relative high induced current caused by the alternating magnetic fields. This leads to relatively high losses, which means that the quality factor of the integrated inductance (coil) is relatively low. In the gigahertz frequency range, the quality factor is, for example, orders of magnitude lower compared with discrete coils. Since the coil quality factor is an important performance variable of analog circuits, there is a need to improve the quality factor of the coils.
The coil types described above are used in standard CMOS processes, for example. In such processes, a relatively low-impedance substrate is used, which results in the correspondingly low coil quality factors. If a high-impedance substrate is used instead, the losses decrease and the coil quality factor increases. However, a high-impedance substrate can have disadvantageous effects on-an entire series of transistor properties. If high-impedance substrates were used, a standard CMOS process would no longer be possible in any case, and so a different process control would be necessary. However, this is not desirable.
A further possibility for improving the coil quality factor is to remove the substrate material directly below the coil by means of a suitable etching process. A metal layer can then be applied between the coil planes and the substrate. By introducing slots, it is possible to prevent eddy currents, shielding with respect to the substrate being achieved at the same time. However, such a solution has the disadvantage that one metal plane fewer is available for coil turns. Moreover, only slight improvements in the coil quality factor can be achieved therewith.
A further disadvantage of the known coils resides in the relatively large area requirements. The coil geometry shown in FIG. 1 requires an area of 0.3*0.3 mm at an inductance of approximately 9 nHz. If a larger inductance is required, the area requirement rises proportionally.
European published patent application EP 0 725 407 describes a three-dimensional coil which is integrated in a microelectronic circuit and in which the coil axis lies horizontally with respect to the chip surface. The coil has one or more turns. The turns are produced by interconnects of a lower metalization plane and interconnects of an upper metalization plane and also via contacts connecting them. In general, xe2x80x9cviaxe2x80x9d is understood to mean a connection piece between two metal planes. In the prior art solution, the inductance is achieved by means of a core made of material of high permeability, which core is introduced between the interconnects and via contacts and constitutes a fundamental feature of the prior art solution. In the case of the coil geometry disclosed in EP 0 725 407, only a small part of the magnetic field penetrates into the substrate, with the result that the losses associated with this decrease and, consequently, the quality factor of the coil is improved. Despite this advantage, that coil geometry has not been used to date. This is due, for example, to the fact that a semiconductor-compatible core material is not available at the present time. Moreover, at high frequencies, all materials of high permeability exhibit high magnetization-reversal losses, which in turn limit the coil quality factor. Furthermore, the via resistances are too high in the case of the metalization layers that are typically used.
It is accordingly an object of the invention to provide a coil and a coil system for integration into a microelectronic circuit, and also to provide a microelectronic circuit, which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein the coils, or coil systems, having a high quality factor can be produced in a simple and cost-effective manner and be integrated into microelectronic circuits.
With the foregoing and other objects in view there is provided, in accordance with the invention, a coil for integration into a microelectronic circuit on a chip, comprising:
interconnects formed in spatially separate metalization planes of the chip;
at least one turn formed by the interconnects, or at least segments of the interconnects, formed in the spatially separate metalization planes; and
via contacts connecting the interconnects and each being formed from a stack of at least two via elements disposed one above the other.
In other words, the first above object is achieved, in accordance with the invention, by a coil for integration into a microelectronic circuit, having one or more turns, the turn(s) being formed by at least segments of two interconnects, which are formed in metalization planes that are in each case spatially separate from one another, and also the via contacts connecting said interconnect(s) and/or interconnect segments. According to the invention, the coil is formed from a stack of two or more via elements arranged one above the other.
This provides a coil having a high quality factor which can readily be integrated into microelectronic circuits. In terms of its basic construction, the coil according to the invention proceeds from the coil described in EP-A-0 725 407. Owing to the low punch-through of leakage fields into the substrate, high coil quality factors can be realized with such a coil geometry. The formula for the inductance in the case of such a coil geometry reads as follows:
L=xcexc0*xcexcr*A*N2/1 
In this case, xcexc0 is the permeability constant (1.2 Exe2x88x926 H/M) and xcexcr is the relative permeability (approximately 100,000 in the case of ferromagnetic material). A is the cross-sectional area of the coil perpendicular to the coil axis, N is the number of turns, and L is the length of the coil. For these reasons described in relation to the prior art, a magnetic core is dispensed with in the case of the coil according to the invention. Instead, it is a basic concept of the present invention that the cross-sectional area of the coil is enlarged. In the case of the solution described in EP-A-0 725 407, this would necessitate very long interconnects in order to realize areas of approximately 10-20 xcexcm2 given the thicknessesxe2x80x94customary in standard metalizationsxe2x80x94of the via contacts (intermetal dielectrics) of 0.5 xcexcm to 0.3 xcexcm. However, these long interconnects have a correspondingly high bulk resistance, as a result of which the quality factor of the coil is reduced. If a higher number of turns is chosen instead, then the bulk resistance likewise increases in accordance with the longer line length.
By virtue of the novel configuration of the via contacts in the form of stacks with in each case two or more via elements arranged one above the other, the cross section of the coil and thus the quality factor thereof can be increased and improved, respectively, in a simple manner. The effect that can be achieved by using a plurality of stacked via elements as via contact is that a standard metalization can be used for producing the coil. This means that a particularly thick intermetal dielectric with correspondingly deep via contacts does not have to be used for increasing the cross-sectional area. The production of particularly deep via contacts deviating from the standard metalizations would only be possible with the aid of special processes, with the result that the production of such coils would be structurally complicated and cost-intensive. A further advantage of the coil according to the invention is that relatively large coil cross-sectional areas can be achieved with short interconnects. Furthermore, it is possible to dispense with an additional magnetic core which constituted one of the basic prerequisites of the solution disclosed in the above-mentioned European document EP 0 725 407.
In modern silicon technologies, there are usually 4 to 6 metal planes available. This means that the vertical distance between the bottommost and the topmost metal layer (metalization plane) may amount to up to 4 xcexcm. If, in a standard metalization, the connection between upper and lower metalization planes is realized not by axe2x80x94particularly longxe2x80x94via contact, but rather by a stack of via elements lying one above the other, the height of the coil cross-section amounts to precisely said 4 xcexcm. As has already been explained further above, the distance between two interconnects of the coil has been about 0.5 xcexcm to date in the case of known solutions.
In a concrete example, the coil according to the invention may have one or more turns, a turn in each case being formed by interconnect pieces, or interconnects, on a bottommost metalization plane and on a topmost metalization plane and also by the via contactsxe2x80x94serving as vertical connectionsxe2x80x94made of stacks of two or more via elements between said metalization planes.
The via contacts may advantageously be oriented at least essentially perpendicularly to the interconnects and/or interconnect segments.
Constituent parts of a metalization plane may preferably be provided at least between individual via elements of a stack.
Via contacts formed in this way make it possible to use a standard metalization for producing the coil. In this case, it has surprisingly been found that via contacts formed in this way have no disadvantages relative to thicker single-part via contacts that are otherwise necessary.
The interconnect(s) and/or the interconnect segments and also the via contacts preferably delimit the cross section of the coil. This cross-sectional area is determined by the vertical distance between the metalization planes forming the interconnect(s) or the interconnect segments, and also the respective length of the interconnect(s) or interconnect segments on said metalization planes. These lengths can be chosen freely within limits owing to the bulk resistance of the lines. Consequently, with longer line pieces on the corresponding metalization planes, correspondingly larger cross-sectional areas are possible.
The interconnect(s) and/or interconnect segments forming the turn or turns of the coil may advantageously be arranged at a distance of about 4 xcexcm from one another. As has already been mentioned further above, such a distance results for example when there are about 4 to 6 metalization planes available.
In accordance with a further refinement, the interconnect(s) and/or interconnect segments and/or the via elements and/or the constituent parts of a metalization plane that are provided between individual via elements may be formed from copper, in particular from copper deposited electrolytically. When copper is used, the constituent parts have only a low resistance. If copper is used as interconnect material, the resistance of the via contact formed as a stack from two or more via elements also remains low. This resistance may be, for example, 3 xcexa9, in the case of a 0.18 xcexcm technology. By means of n-via stacks this resistance can be reduced to 1/n by means of connection in parallel. If a standard metalization with copper is used to produce the coil, it is also possible, for example, during this method, to fill the vertical connection pieces between the metal planes (the via elements) with the low-impedance copper.
In accordance with a particularly advantageous feature of the invention, copper deposited by means of an electrolytic method is used. This production of the copper is already known per se. It is described, for example in the paper xe2x80x9cCopper Electroplatingxe2x80x9d by Alexander E. Braun, which was published in the journal xe2x80x9cSemiconductor Internationalxe2x80x9d, April 1999, page 58 et seq., and whose disclosure content is in this respect incorporated in the description of the present invention.
The coil may advantageously be formed for integration in a microelectronic circuit arranged on and/or in a substrate, the coil axis being oriented horizontally with respect to the substrate surface. This makes it possible to reduce the punch-through of leakage fields into the substrate, which leads to higher coil quality factors.
The coil start and the coil end of the coil may preferably be arranged adjacent to one another with the result that the coil axis forms an at least approximately closed line, in particular a circular line. Such a form of the coil axis reduces the leakage losses, which leads to a further improvement in the coil quality factor. Particularly when the coil axis forms an approximately circular line, this geometry allows the coil to be shielded laterally in a suitable manner, as will be explained in more detail as the description progresses with regard to the coil system according to the invention.
The second above object is achieved with a coil system for integration in a microelectronic circuit, which, according to the invention, is characterized by one or more coils according to the invention as described above. With regard to the advantages, actions, effects and the method of operation of the coil system according to the invention, reference is likewise made to the entire contents of the above explanations concerning the coil according to the invention, and they are hereby incorporated by reference.
Preferably, for the shielding of the coil(s), provision is made of a number of via stacks each formed from one or more via element(s). These via stacks are advantageously arranged outside the coil(s), in particular outside the coil periphery, around the latter. If a whole series of via stacks are arranged next to one another, placed around a coil, then efficient lateral shielding of the coil can thereby be achieved.
In accordance with an added feature of the invention, the via stacks are oriented approximately perpendicularly to the coil axis.
In accordance with a further refinement of the invention, there is provided at least one shielding plane for the vertical shielding of the coil.
By way of example, the shielding plane may be formed as a metal plane.
In a further refinement, the shielding plane may be formed as a polysilicon area or as a structure with a highly doped substrate.
If there are sufficient metalization planes available, then the topmost metalization plane may be used, for example, as a shielding plane for vertical shielding of the coil toward the top. This metal plane may preferably be formed as a slotted area in order to prevent eddy currents. For shielding of the coil toward the bottom, use may be made, for example, of a shielding plane which is formed as a polysilicon layer or a structure with a highly doped substrate. This lower shielding plane may also advantageously be formed as a slotted area.
The invention, furthermore, provides for a microelectronic circuit, having a number of integrated components, at least one of these components being formed as an inductance. According to the invention, the microelectronic circuit is characterized by the fact that the component provided as an inductance is formed as a coil according to the invention as described above and/or as a coil system according to the invention as described above. This makes it possible to create microelectronic circuits in which coils, or coil systems, having a high quality factor can be integrated, so that such microelectronic circuits can also be used at very high frequencies in ranges far above 1 GHz. With regard to the advantages, actions, effects and the method of operation of the microelectronic circuit according to the invention, reference is likewise made to the entire contents of the above explanations concerning the coil according to the invention, and also the coil system according to the invention, and they are hereby incorporated by reference.
The microelectronic circuit may advantageously be formed on and/or in a chip, the chip being formed from a substrate and at least one oxide layer.
The coil, for example the coil system, may preferably be arranged within the oxide layer. In this way, it is possible to resort to a standard metalization during the production of the coil.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a coil and coil system for integration into a micro-electronic circuit and microelectronic circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.